1. Technical Field
The invention relates to the field of solid state image sensors, and more particularly to CMOS and CCD image sensor generated carrier to voltage conversion with high sensitivity and no kTC noise generation.
2. Background Art
Silicon based solid state CMOS and Charge Coupled Device (CCD) image sensors are particularly suitable for imaging in the visible spectrum. These image sensors are based on monolithic focal plane arrays which may have up to 100 million densely packed photodetectors, and a read-out multiplexer. The detector array samples the image by segmenting it into a two dimensional array of analog samples, where each photodetector provides an analog charge signal (or sample) proportional to the optical signals received by the photodetector. This arrangement yields a two dimensional densely packed array of analog charge samples that are processed by a CMOS or CCD read-out multiplexer. In addition to the x-y photodetector address function, the multiplexer converts the generated analog charge signal into a voltage. This charge-to-voltage read-out transduction is a very important operation for it determines the sensor's sensitivity, and operating speed. Accordingly, much attention is given to transduction of photons from the scene into analog voltage signals. The transduction process includes two steps: conversion of photons into charges, and conversion of charges into analog output voltage signal. With silicon, converting photons into charge signal is done directly by interband electron-hole excitation. This conversion process is a very efficient, low noise, and high speed process, and it alleviates the need for electrical injection of photosignals into CCD or CMOS devices. Conversion of generated charges into output voltage signal is more difficult and has a major impact on the imager's performance. Similarly, CCD signal, processors need transducers to convert charge signals to analog output voltages. Consequently, whether the charge signals are generated by photons or an electrical circuit, much attention has been focused on optimizing the charge-to-voltage read-out structures.
Conventional charge-to-voltage read-out circuits fall into two broad categories: destructive read-out and non-destructive read-out (NDRO). Destructive charge read-out uses a Field-Effect-Transistor (FET) to convert the charge to a voltage signal and is used with both CMOS and CCD imagers. The approach is to deposit directly, or indirectly, the signal charge on a precharged floating diffusion that is part of a p/n junction. The charge changes the DC potential of the diffusion and a FET gate is used to sense this change. Read-out of many charge signals, with the same structure, is achieved by resetting the floating diffusion after each read-out operation. The approach for destructive read-out for a CMOS imager is the same as is used in a CCD. However the CCD's destructive read-out also incorporates charge transfer. A disadvantage of the destructive charge read-out method is that charging and discharging the FET gate's capacitance for read-out gives rise to kTC reset noise. The kTC reset noise is removed using the Correlated-Double-Sampling (CDS) technique and this has significantly improved the performance of destructive charge read-out. However, the inclusion of CDS circuits in the imaging system adds complexity and the technique is particularly difficult to apply at high frequencies. An advantage of the destructive charge read-out structure is the relative ease of fabrication that utilizes existing CCD and CMOS imager semiconductor processing technology.
In the NDRO approach, the charge signal inside a potential well is sensed electrostatically. The NDRO does not have kTC reset noise since the charge sensed is in a potential well and not on a capacitor's plate. Removal of the charge after sensing is by clocking the potential well wherein the charge resides. Clocking the potential well is different than removing charge present on a capacitor plate with a reset switch. In conventional destructive readout structures, removing charge from a capacitor's plate is with a rest switch and the switches' resistance gives rise, to kTC reset noise. NDRO charge read-out circuits remove charge after sensing by clocking potential wells, and are more compact than destructive charge read-out circuits. Early mechanization of NDRO's (see FIG. 1A) was with floating gate 109 incorporated within the CCD clocking gates. The floating gate's potential VFG, changes as signal charge QCCD is transported below and within the CCD channel. Changes in the floating gate's potential δVFG is related to the signal charge QCCD by,
                              δ          ⁢                                          ⁢                      V            FG                          =                                            Q                              CCD                ⁢                                                                                        ⁢                                                  ⁢            1                                              C              1                        ⁡                          (                              1                +                                                      C                    CN                                                        C                    1                                                  +                                                      C                    CN                                                        C                    2                                                              )                                                          (        1        )            where C1 is the capacitance between the floating gate 109 and the CCD clocking gate; C2 is the capacitance between the floating gate and the charge packet 110; and CCN is the capacitance between the charge packet and the CCD substrate. Making CCN<<(C1 and C2) maximizes the voltage signal δVFG, for a given charge signal QCCD. A significant advantage of this NDRO structure is the elimination of “kTC” reset noise. The NDRO structure's output varies with the charge QCCD, and this charge is moved with CCD clocking gates. The signal charge QCCD is completely removed, from under the floating gate 109, by manipulating the CCD potential wells, and this corresponds to a complete reset of the NDRO. This is unlike the reset of a capacitor through a switch with on resistance, which leaves a (kT/C)1/2 reset noise voltage on the capacitor. In the NDRO, the signal charge QCCD is completely removed by the CCD charge transfer thereby eliminating kTC reset noise. Noise wise this is a significant performance advantage. However, there are several disadvantages with this NDRO approach. First, limited shielding allows electrical coupling between the clock pulses, operating the CCD gates, and the floating gate 109, causing a corruption of the NDRO's output, signals. Second, this structure is difficult to fabricate, and the DC potential of the floating gate 109 is difficult to control. Controlling the potential of the floating gate is the most serious issue. It may be controlled by periodic reset of the floating gate. However, reset will introduce kTC reset noise thereby eliminating a major advantage to this specific NDRO approach. Instead of periodic reset, a very large resistor can be used to control the MIS gate's potential. However, it is very difficult to incorporate very large resistors into the CCD fabrication process.
The gate's 109 potential problems can be circumvented by replacing the floating gate with a FET that is built directly into the CCD channel. Incorporating a depletion mode FET into the CCD channel (see FIG. 1B) eliminates the floating gate issues and several associated problems. Charge sensing is produced by changes in the depletion width between the CCD channel and the FET. As the generated charge packet QCCD increases, the depletion width decreases, making the FET more conductive. This sensing effect is analogous to using a back gate to modulate the FET. It should be evident that replacing the depletion mode FET by a surface channel device (see FIG. 1C) will also sense QCCD in the CCD channel. However, with a surface channel FET, the coupling to the CCD charge is very poor resulting in low charge-to-voltage conversion gain. A close proximity between the NDRO surface channel FET and the CCD signal charge should reduce the effects of fixed pattern noise due to electrical feed-throughs. The benefits offered with the prior art NDRO structures are mitigated by increased fabrication difficulties and issues related to the NDRO's transfer function, which converts the signal charge to a voltage signal. With the invention of CDS, the NDRO's advantage has been reduced and destructive CCD read-out structures, using a floating diffusion, have gained dominance.
It is therefore desirable to provide an NDRO structure capable of high sensitivity charge-to-voltage read-out, no kTC read-out noise, and a simplified fabrication that utilizes existing CCD and CMOS imager semiconductor processing technology. It should be noted that while a number of noteworthy advances and technological improvements have been achieved within the art of CCD and CMOS charge-to-voltage read-out circuits, none completely fulfill the specific objectives achieved by this invention.